In a case where a data read request is received externally, NAND type flash memory (hereinbelow, NAND memory) that is one of storage devices synchronizes requested data (read data) with a data latch signal (clock signal that becomes a reference of timing to latch data) and outputs the same. In a memory controller, a predetermined amount of delay is added to the data latch signal imputed from the NAND memory, and data is latched at timing that is synchronized with the data latch signal after the addition of the delay (hereinbelow referred to as a delayed data latch signal). For example, the data is latched at a rising edge of the delayed data latch signal. Further, a toggle mode by which the data can be read at faster speed also exists. In the toggle mode, the data is latched at both edges (rising edge and trailing edge) of the delayed data latch signal. A conventional memory controller includes a delay element, and the delay element generates a delayed data latch signal by delaying the data latch signal by a fixed delay amount that is predetermined set.
Data transfer speed of the NAND memory is becoming faster than ever, and accompanying this, a valid period during which read data can be latched is becoming shorter. Due to this, it is gradually becoming difficult to preset the delay amount to be given to the data latch signal and generate the delayed data latch signal by the delay element giving delay to the data latch signal. That is, even if the delay amount is set upon production, the delay time of the delay element changes by a peripheral temperature and operation voltage fluctuation and the like of an apparatus that installs the NAND memory, and a possibility that the read data cannot be latched within the valid period (not being able to correctly read data) is growing.